1. Field of the Invention
The present invention relates to circuit devices having a plurality of circuit elements mounted therein, and it particularly relates to a circuit device in which a plurality of circuit elements are multilayered.
2. Description of the Related Art
Portable electronics devices, such as mobile phones, PDAs, DVCs and DSCs, are today gaining higher functions at an accelerated pace. For them to be accepted by the market, however, such products must be small and lightweight. To achieve that, system LSIs of high integration are much in demand. On the other hand, what is required of these electronics devices is handiness and ease of use, and consequently the demand is high for the high function and high performance of LSIs used in these devices. As a result, while the number of I/Os increases along with the higher integration of LSI chips, there is an increasing demand for smaller packages. To reconcile these mutually conflicting demands, it is strongly desired that semiconductor packages be developed that are suited to the high-density board mounting of semiconductor parts.
A known packaging technology to meet these demands for higher density is a multiple stack structure for the multilayering of circuit elements. Such circuit elements are to be noted to include elements such as semiconductor chips. Reference (1) in the following Related Art List discloses a circuit device with bottom-layer semiconductor chips wire-bonded to the substrate.
Reference (2) in the following Related Art List discloses a circuit arrangement with the bottom-layer semiconductor chip flip-chip-bonded to the substrate.
FIG. 13 is a cross-sectional view showing a structure of a circuit device disclosed in Reference (1). The lower-layer semiconductor chip 3 and the upper-layer semiconductor chip 4 are stacked in a vertical direction, and a heat-transfer conductive layer 5 is interposed between the lower-layer semiconductor chip 3 and the upper-layer semiconductor chip 4. The lower-layer semiconductor chip 3 and the upper-layer semiconductor chip 4 are connected to the wiring layer of the substrate 2 by means of bonding wire 7 and bonding wire 8, respectively. The heat-transfer conductive layer 5 is connected to the ground wiring of the substrate 2.
FIG. 14 is an equivalent circuit diagram showing the states of potentials during the operation of the circuit elements as disclosed in Reference (1). The voltage drop due to a resistance component occurring in the bonding wire 7 for grounding is the potential difference V1′ between the ground potential of the lower-layer semiconductor chip 3 and the ground potential of the substrate 2. The voltage drop due to the resistance component and inductance component occurring in the bonding wire 7 for power supply is the potential difference V2′ between the power supply potential of the lower-layer semiconductor chip 3 and the power supply potential of the substrate 2. The voltage drop caused by a circuit provided on the lower-layer semiconductor chip 3 is denoted by V3′. It is to be noted that the inductance components of L1′, L2′, L4′ and L5′ shown in FIG. 14 are the causes of noise amplification.
On the other hand, the voltage drop due to a resistance component occurring in the bonding wire 8 for grounding is the potential difference V4′ between the ground potential of the upper-layer semiconductor chip 4 and the ground potential of the substrate 2. The voltage drop due to the resistance component occurring in the bonding wire 8 for power supply is the potential difference V5′ between the power supply potential of the upper-layer semiconductor chip 4 and the power supply potential of the substrate 2. The voltage drop caused by a circuit provided on the upper-layer semiconductor chip 4 is denoted by V6′.
Related Art List
    (1) Japanese Patent Application Laid-Open No. 2004-111656.    (2) Japanese Patent Application Laid-Open No. Hei11-204720.
In a conventional circuit arrangement as represented in Reference (1), there are cases where noise having a high-frequency component occurring at the ground potential of the upper-layer semiconductor chip is propagated to the ground wiring of the substrate as indicated by arrow A in FIG. 14. This noise component affecting the lower-layer semiconductor chip via the ground wiring has been a factor of destabilizing the operation of the circuit device, thus causing a drop in reliability. Hereinbelow, the noise propagating through the ground wiring is referred to as ground noise.